Non-volatile semiconductor memory cells using a floating gate to store charges thereon and arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type or stacked gate type. The memory cell utilizes a control gate that is spaced apart and insulated from a floating gate. The control gate can further include a select gate portion. A layer of insulating material (e.g. oxide) is formed between the floating gate and control gate. The thickness of this oxide layer is important because it dictates the level of capacitive coupling between the two gates and it must be thin enough to allow Fowler-Nordheim tunneling for those cells that are erased by tunneling electrons from the floating gate to the control gate.
Typically such memory cells are formed in an array configuration, with peripheral circuitry also formed on the same semiconductor die. The peripheral circuitry often includes one or more high voltage MOS transistors for operating the memory cell array. FIG. 1 illustrates a conventional memory cell 1 from the memory cell area of the die, as well a conventional high voltage MOS transistor 2, all formed on the same semiconductor die 3. The memory cell 1 is a split gate type memory cell. A tunneling oxide layer 4 is formed between the control gate CG and the floating gate FG, with source S and drain D regions formed in the substrate. The transistor 2 includes a poly gate PG that is insulated from the substrate 3 by a gate oxide 5, and overlaps with source S and drain D, where the poly gate PG controls the conductivity of the channel region between the source S and drain D.
Processing efficiency is important in the fabrication of semiconductor devices. Therefore, it is desirable to fabricate corresponding memory and transistor elements using the same processing steps. Thus, the memory cell control gates CG and the transistor poly gates PG are preferably formed using the same polysilicon deposition step. Likewise, the formation of the memory cell tunnel oxide 4 and the transistor gate oxide 5 is formed using the same oxide formation step.
FIGS. 2A to 2D illustrate a conventional method of forming a memory cell in the memory cell area 6 of substrate 3, and a MOS transistor in the peripheral area 7 of substrate 3. Silicon dioxide (hereinafter “oxide”) layer 8, polysilicon (hereinafter “poly”) layer 9, and silicon nitride (hereinafter “nitride”) layer 10 are first formed over the substrate 3. A masking step is used to selectively etch and remove a portion of nitride layer 10, forming a hole 11 that exposes the poly layer 9. The structure is oxidized to form oxide layer 12 over the exposed portion of poly layer 9 at the bottom of hole 11. The resulting structure is shown in FIG. 2A.
Next, a series of etches are used to remove nitride layer 10, and those portions of poly layer 9 and oxide layer 8 not protected by oxide layer 12, as shown in FIG. 2B. Oxide layer 13 is then formed over the structure, followed by the formation of nitride spacers 14, as shown in FIG. 2C. Finally, a poly deposition and masking step is used to form poly block 15 on oxide layer 13 (laterally adjacent and vertically over poly layer 9), and poly block 16 on oxide layer 13 (in peripheral area 7). Ion implantation is used to form source regions 17 and drain regions 18, as shown in FIG. 2D. Poly block 15 forms the memory cell control gate, poly layer 9 forms the memory cell floating gate, and the portion of oxide layer 13 therebetween forms the memory cell tunnel oxide. Poly block 16 forms the transistor poly gate, and the portion of oxide layer 13 underneath poly block 16 forms the gate oxide for the transistor.
This fabrication process illustrates how the oxide layer 13 serves as both the tunnel oxide for the memory cell 1 and the gate oxide for the transistor 2. Thus, the thickness of the tunnel and gate oxides is necessarily the same. However, this is not ideal for devices in which the MOS transistor 2 operates at a higher voltage than does the memory cell 1.